The Research on Indirect Frequency Synthesizer of Low Phase Noise Digit PLL 低相噪数字锁相间接频率合成器的研究
To meet the need of research on some sonar system, the paper designs a digital torpedo noise simulator, which can conveniently provide real-time and multi-parameter sonar signals in the digit. 本文针对某型声纳的研制需要,设计开发了一种数字鱼雷噪声模拟器。
This paper analyzes phase noise of digit PLL frequency synthesizer in detail, emphasises design of low phase and spurious PLL ′ s loop filter with control theory, and the viewpoint has been testified with results of S band synthesizer. 较详细地分析数字锁相频率合成器的相位噪声,着重用控制论方法对低相噪、低杂波锁相环的环路滤波器进行设计,并用某S波段频率合成器的实验结果进行了验证。
It can produce broad-band white noise which has normal distribution, digit noise, and digit increment noise. 它能够产生正态分布的宽带自噪声、数字噪声和数字增量噪声。
Several key techniques including real time noise reduction, design of algorithms and sign digit, time allocation for all working parts, and clock synchronizing with a background of high noise are investigated. 研究了实时去噪的几项关键技术、算法和符号位的设计,各部分工作时间分配以及大背景噪声下时钟同步方法。
Low Phase Noise and Spurious Digit PLL ′ s Loop Filter Design 低相噪、低杂波数字锁相环路滤波器的设计